The present invention relates to semiconductor design technology, and more particularly, to a power supply controller of a cell array block in a semiconductor memory device.
In general, an operational mode of a semiconductor memory device such as a dynamic random access memory (DRAM) or the like is divided into two modes, of which one is an active mode and the other is a stand-by mode. When the semiconductor memory device is in the active mode, circuits in a chip operate to output requested data to the outside or to receive required data thereinto. Meanwhile, when the semiconductor memory device is in the stand-by mode, all current paths of circuits are cut off to minimize power consumption in the chip except for minimum number of circuits that are enabled to enter the active mode.
However, when the semiconductor memory device keeps in the stand-by mode for a long time, the circuits, which are enabled to enter the active mode, consume unnecessary current continuously. In particular, off leakage current mainly accounts for such an unnecessary current consumption in a transistor that uses a boosted voltage VPP with high voltage level as a bias voltage.
In addition, a transistor using the boosted voltage VPP, which is applied to an unselected cell array block in a bank even during the active mode, as the bias voltage also generates the large amount of off leakage current undesirably as similar to the above. Herein, the cell array block is selected by a cell array select signal generated corresponding to a column address. Since the boosted voltage VPP has a high voltage level, high electric field is applied across a source and a drain of a transistor, which causes the large amount of off leakage current to be generated. Furthermore, this phenomenon of the off leakage current also occurs during a self-refresh mode including a stand-by mode.
FIG. 1 is a block diagram of a conventional cell array block.
Referring to FIG. 1, the conventional cell array block includes a plurality of matrix blocks 11 having a plurality of memory cells, a plurality of sub hall regions 10, and a plurality of X-decoders 12. The sub hall region 10 is provided with a main word line driver, a bit line sense amplifier (BLSA) driver, and a bit line isolation transistor.
The boosted voltage VPP is applied to the matrix blocks 11, the sub hall regions 10, and the X-decoders 12, respectively. Also, the boosted voltage VPP is used as a substrate bias voltage VBB.
Here, a supply mechanism of the boosted voltage VPP will be described below by using, for example, a generator for generating bit line isolation transistor (BLIT) control signals BISHB/BISH (hereinafter, referred to as ‘BLIT control signal generator’ for simplicity) which is provided in the sub hall region 10. Although this boosted voltage supply mechanism is also applied to transistors (drivers) using the boosted voltage VPP as well as the BLIT control signal generator, following illustration focuses on the BLIT control signal generator for convenience of description.
FIG. 2 is a circuit diagram of the BLIT control signal generator.
Referring to FIG. 2, the BLIT control signal generator has an inverter structure provided with a PMOS transistor P1 and an NMOS transistor N1.
When an input signal of a bit line isolation bar signal BISHB is at a logic low level, the PMOS transistor P1 is turned on to output a bit line isolation signal BISH by the boosted voltage VPP. The boosted voltage VPP is also applied as the substrate bias voltage.
This is the same in both the active mode and the stand-by mode. In these modes, high electric field is applied across the source and the drain of the PMOS transistor P1, causing the large amount of off leakage current to be generated.
That is, great amount of off leakage current is generated because the boosted voltage with high voltage level is applied to a cell array block which is not selected by a cell array block select signal during the active mode or the stand-by mode. As described above, the cell array block select signal is generated by a column address signal, and selects some of the plurality of cell array blocks.
Therefore, it is required a control circuit that can apply a voltage having a voltage level lower than that of the boosted voltage VPP to only the cell array block that is not selected by the cell array block select signal. Here, it is noticed that an extremely low voltage cannot be used as the voltage to be applied to the unselected cell array block because the extremely low voltage must be raised to a level of the boosted voltage VPP when a corresponding cell array block is selected. That is, a response time must be delayed when using the voltage extremely lower than the boosted voltage VPP. Thus, the voltage to be applied to the unselected cell array block must have a predetermined voltage level in consideration of both the off leakage current and the response time.